Search all intrinsics
SIMD ISAReturn TypeNameArgumentsInstruction Group
Heliumint8x16_t[__arm_]vcreateq_s8(uint64_t a, uint64_t b)Vector manipulation / Create vector
Description
Creates a vector with a register representation the same as the concatenation of two 64-bit values.
Results
Qd result
This intrinsic compiles to the following instructions:

VMOV Qd[0], Rt0

VMOV Qd[1], Rt1

VMOV Qd[2], Rt2

VMOV Qd[3], Rt3

Argument Preparation
a register: [Rt, Rt2]b register: [Rt3, Rt4]
Architectures
MVE